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precision wide range (3 na to 3 ma) high-side current mirror ADL5315 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features accurately mirrors input current (1:1 ratio) over 6 decades linearity 1% from 3 na to 3 ma stable mirror input voltage voltage held 1 v below supply using internal reference or can be set externally adjustable input current limit 2.7 v to 8 v single-supply operation miniature 8-lead lfcsp (2 mm 3 mm) applications optical power monitoring from a single photodiode general voltage biasing with precision current monitoring voltage-to-current conversion functional block diagram voltage reference current limiting comm vset nc inpt i pd current mirror 1:1 ADL5315 4 2 7 sref 3 1 6 vpos 20k 5 rlim 8 iout i pd 05694-001 figure 1. general description the ADL5315 is a wide input current range, precision high-side current mirror featuring a stable and user-adjustable input voltage. it is optimized for use with pin photodiodes, but its flexibility and wide operating range make it suitable for a broad array of additional applications. over the 3 na to 3 ma range, the current sourced from the inpt pin is accurately mirrored with a 1:1 ratio and sourced from the iout output pin. in a typical photodiode application, the output drives a current- input logarithmic amplifier to produce a linear-in-db output representing the optical power incident upon the photodiode. for linear voltage output, a single resistor to ground is all that is required. the photodiode anode can be connected to a high speed transimpedance amplifier for the extraction of the data stream. the voltage at the inpt pin is temperature stable with respect to the voltage at the vset input pin, which it tracks. a temperature stable reference voltage is provided at the sref pin, which, when tied to vset, fixes the voltage at inpt 1.0 v below vpos. vset can also be driven from an external source. the vset input has very low input current and can be driven as low as the bottom rail, facilitating nonloading voltage-to- current conversion as well as minimizing dark current in photodiode applications. the ADL5315 also features adjustable input current limiting using an external resistor from rlim to vpos. the maximum current sourced by inpt (and iout) can be set between 1 ma and 16 ma, beyond which the voltage at inpt falls rapidly from its setpoint. connecting rlim directly to vpos provides basic input short-circuit protection with the default current limit of 16 ma typical. the ADL5315 is available in a 2 mm 3 mm, 8-lead lfcsp and is specified for operation from ?40c to +85c.
ADL5315 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 4 esd caution.................................................................................. 4 pin configuration and function descriptions............................. 5 typical performance characteristics ............................................. 6 theory of operation ........................................................................ 9 bias control interface .................................................................. 9 noise performance ..................................................................... 10 mirror response time............................................................... 10 input current limiting.............................................................. 10 applications..................................................................................... 11 average power monitoring ....................................................... 11 translinear log amp interfacing............................................. 12 extended operating range....................................................... 13 using rlim as a secondary monitor ...................................... 13 characterization methods ........................................................ 14 evaluation board ............................................................................ 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revision history 10/05revision 0: initial version
ADL5315 rev. 0 | page 3 of 20 specifications v pos = 5 v, v set = 4 v, i inpt = 3 a, t a = 25c, unless otherwise noted. table 1. parameter conditions min typ max unit current mirror output iout (pin 8) current gain from inpt to iout 0.99 1.00 1.01 current gain from inpt to iout ?40 c < t a < +85 c 0.97 1.00 1.03 a/a nonlinearity 3 na < i pd < 3 ma 0.25 1.00 % small signal bandwidth i inpt = 3 na 1 khz i inpt = 3 a 1 mhz wideband noise at ipdm i inpt = 3 a, c set = 2.2 nf 20 na rms specified output voltage range 0 v pos ? 1 v i out r out product i inpt = 3 a 900 v mirror input, voltage control inpt (pin 1), vset (pin 2), sref (pin 3) specified input current range, i inpt flows from inpt pin 3n 3m a specified vset voltage range 2.7 v < v pos < 6.5 v 0 v pos ? 1 v 6.5 v < v pos < 8 v v pos ? 6.5 v pos ? 1 v incremental gain from vset to inpt 0.2 v < v set < 7.0 v 0.98 1 1.02 v/v incremental input resistance at vset v set = 4.0 v >100 g input bias current at vset v set = 4.0 v <30 pa sref voltage, relative to v pos 2.7 v < v pos < 8 v ?1.04 ?1.0 ?0.97 v overcurrent protection inpt current limit v inpt drops to 0 v, r lim = 0 16 ma v inpt drops to 0 v, r lim = 3 k 6.4 8 9.6 ma power supply vpos (pin 6) supply voltage range 2.7 8 v quiescent current i inpt = 3 a 1.8 2.2 ma i inpt = 3 ma 8.3 10.2 ma
ADL5315 rev. 0 | page 4 of 20 absolute maximum ratings table 2. parameter rating supply voltage 8 v input current at inpt 20 ma internal power dissipation 500 mw ja (soldered exposed paddle) 80c/w maximum junction temperature 125c operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ADL5315 rev. 0 | page 5 of 20 pin configuration and fu nction descriptions nc = no connect 1inpt 2vset 3sref 4comm 8 iout 7nc 6 vpos 5 rlim top view (not to scale) ADL5315 05694-002 figure 2. 8-lead lfcsp table 3. pin function descriptions pin o. neonic description 1 inpt input current. pin sources current only. 2 vset sets voltage at inpt (gain = 1). range 0 v to v pos ? 1.0 v for v pos < 6.5 v. for v pos 6.5 v range, v pos ? 6.5 v to v pos ? 1 v. optional shielding of inpt trace. 3 sref reference voltage for vset. internally generated at v pos ? 1.0 v through 20 k. can be shorted to vset for standard mirror operation. 4 comm analog ground. 5 rlim external resistor to vpos. sets cu rrent limit at inpt from 1 ma to 16 ma. i lim = 48 v/(r lim + 3 k). 6 vpos positive supply (2.7 v to 8.0 v). 7 n/c optional shielding of iout trace. no connection to die. 8 iout output current. mirrors current at inpt with a gain of 1.0. sources current only. paddle internally connected to comm, solder to ground.
ADL5315 rev. 0 | page 6 of 20 typical performance characteristics v pos = 5 v, v set = v sref , v out = 0 v, t a = 25c, unless otherwise noted. 2.0 ?2.0 1n 10m i inpt (a) linearity (%) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 10m 1n i out (a) 1m 100 10 1 100n 10n 10n 100n 1 10 100 1m ?40 c +25 c +70 c +85 c 0 c +25 c, +70 c, +85 c, 0 c, ?40 c 05694-003 figure 3. i out linearity vs. i inpt for multiple temperatures, normalized to 25c and i inpt = 3 a 10m 1 10 100 1m 3 ?3 1n i inpt (a) linearity (%) 05694-021 10n 100n +85 c +25 c ?40 c 2 1 0 ?1 ?2 figure 4. i out linearity vs. i inpt for multiple temperatures and devices normalized to 25c and i inpt = 3 a 10m 3.0 0 1n i inpt (a) wideband current noise (%) 05694-016 2.5 2.0 1.5 1.0 0.5 10n 100n 1 10 100 1m v pos = 3.0v v pos = 4.6v v pos = 7.8v figure 5. output wideband current noise as a percentage of i out vs. i inpt for multiple values of v pos , c set = 2.2 nf, bw = 10 mhz 2.0 ?2.0 1n 10m i inpt (a) linearity (%) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 10m 1n i out (a) 1m 100 10 1 100n 10n 10n 100n 1 10 100 1m i inpt vs. i out , all voltage conditions v pos = 2.7v, v set = v sref v pos = 5v, v set = 2v v pos = 5v, v set = v sref v pos = 8v, v set = 2v v pos = 8v, v set = v sref 05694-006 figure 6. i out linearity vs. i inpt for multiple supply conditions, normalized to v pos = 5 v, v set = v sref , and i inpt = 3 a 10m 1 10 100 1m 40 ?120 1n i inpt (a) v inpt variation (mv) 0 ?40 ?80 05694-005 20 ?20 ?60 ?100 10n 100n ?40 c, v pos = 2.7v, v set = v sref ?40 c, v pos = 5v, v set = 0v ?40 c, v pos = 5v, v set = v sref +25 c, v pos = 2.7v, v set = v sref +25 c, v pos = 5v, v set = 0v +25 c, v pos = 5v, v set = v sref +85 c, v pos = 2.7v, v set = v sref +85 c, v pos = 5v, v set = 0v +85 c, v pos = 5v, v set = v sref figure 7. v inpt variation vs. i inpt for multiple temperatures and voltage, normalized to v pos = 5 v, v set = v sref , i inpt = 3 a and 25c 10mhz 1na 1fa 100hz frequency nsd (a rms/ hz) 05694-007 100pa 10pa 1pa 100fa 10fa 1khz 10khz 100khz 1mhz 3.6ma 360 a 36 a 3.6 a 360na 36na 3.6na figure 8. output current noise density vs. frequency for multiple values of i inpt , v pos = 4.6 v, v set = v sref , c set = 2.2 nf
ADL5315 rev. 0 | page 7 of 20 +3 sigma ?3 sigma average 20 ?20 ?40 temperature ( c) v inpt drift (mv) 05694-019 90 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 15 10 5 0 ?5 ?10 ?15 figure 9. temperature drift of v inpt with v set = v sref , 3- to either side of mean 10 ?40 100 1000m frequency (hz) normalized response (db) 1k 10k 100k 1m 10m 100m 05694-008 5 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 30na 300na 30 a 3 a 300 a 3ma 3na figure 10. small-signal ac response of i inpt to i out for i inpt in decades from 3 na to 3 ma 4.5 ?1.0 0 10 time (ms) v inpt (v) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 123456789 05694-018 t-rise for all currents 200ns 100na t-fall 9.5ms 10 a t-fall 180 s 1ma t-fall 600ns figure 11. pulse response of v set to v inpt (v set pulsed from 0 v to 4 v) for multiple values of i inpt +3 sigma ?3 sigma average 20 ?20 ?40 temperature ( c) v inpt drift (mv) 05694-022 90 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 15 10 5 0 ?5 ?10 ?15 figure 12. temperature drift of v inpt with v set = 4 v (external voltage source), 3- to either side of mean 400 10m 1n 0 time ( s) i out (a) 05694-017 1m 100 10 1 100n 10n 50 100 150 200 250 300 350 300 a to 3ma: t-rise = <10ns, t-fall = <300ns 30 a to 300 a: t-rise = <10ns, t-fall = <300ns 3 a to 30 a: t-rise = <10ns, t-fall = <1 s 300na to 3na: t-rise = <20ns, t-fall = <5 s 30na to 300na: t-rise = <5 s, t-fall = <25 s 3na to 30na: t-rise = <100 s, t-fall = <200 s figure 13. pulse response of i inpt to i out for i out in decades from 3 na to 3 ma 100 10 ?10 0 r lim (k ) error from calculated current limit (%) 05694-020 0 v pos = 2.7v, v set = v sref v pos = 5v, v set = v sref v pos = 8v, v set = v sref 8 6 4 2 ?2 ?4 ?6 ?8 10 20 30 40 50 60 70 80 90 i lim = 48/(r lim + 3k ) figure 14. current limit error in percent vs. r lim for multiple voltages
ADL5315 rev. 0 | page 8 of 20 1.010 0.990 2 8 v pos (v) v pos ? v inpt (v) 1.005 1.000 0.995 3 +85 +25 ?40 4567 05694-004 figure 15. v pos ? v inpt vs. v pos for multiple temperatures 25 0 0.99 i out /i inpt (a/a) (%) 20 15 10 5 0.993 0.996 0.999 1.002 1.005 1.008 05694-032 n = 2014 mean = 1.00251 sd = 0.00175921 figure 16. distribution of i out /i inpt for v pos = 5 v, v set = 4 v, and i inpt = 3 a 35 0 ?0.97 ?1.03 v sref ? v pos (v) (%) 30 25 20 15 10 5 ?0.98 ?0.99 ?1.00 ?1.01 ?1.02 05694-033 n = 2027 mean = ?1.00696 sd = 0.00389073 figure 17. distribution of v sref ? v pos for v pos = 5 v and i inpt = 3 a 25 0 ?0.03 0.03 v set ? v inpt (v) (%) 20 15 5 10 ?0.02 ?0.01 0 0.01 0.02 05694-034 n = 2034 mean = 0.00122744 sd = 0.00403179 figure 18. distribution of v set ? v inpt for v pos = 5 v, v set = 4 v, and i inpt = 3 a
ADL5315 rev. 0 | page 9 of 20 theory of operation the ADL5315 addresses the need for precision high-side monitoring of photodiode current in fiber optic systems and is useful in many nonoptical applications as well. it is optimized for use with adis family of translinear logarithmic amplifiers, which take advantage of the wide input current range of the ADL5315. this arrangement allows the anode of the photo- diode to connect directly to a transimpedance amplifier for the extraction of the data stream without the need for a separate optical power monitoring tap. figure 19 shows the basic connections for the ADL5315. ADL5315 comm vset nc voltage supply mirror current output inpt 4 2 7 sref 3 1 6 vpos 5 rlim 8 iout 0.01 f 0.1 f 2.2nf r lim 390pf 4k 05694-023 figure 19. basic connections at the heart of the ADL5315 is a precision 1:1 current mirror with a voltage following characteristic that provides an adjustable bias voltage at the mirror input. this architecture uses a jfet input amplifier to drive the bipolar mirror and maintain stable v inpt voltage, while offering very low leakage current at the inpt pin. the current sourced by the low impedance inpt pin is mirrored and sourced by the high impedance iout pin. bias control interface the voltage at the inpt pin, v inpt , is forced to be equal to the voltage applied to vset by the mirror-biasing loop. the v set voltage range extends down to ground, allowing the ADL5315 to be used as a voltage-to-current converter with a single resistor from inpt to ground. this capability allows dark current to be minimized in pin photodiode systems by maintaining a small voltage bias. the vset control also allows v inpt to be set approximately equal to the load voltage at iout. balancing the mirror voltages in this way provides inherently superior linearity over the widest current range independent of the supply voltage. only leakage currents from the jfet op amp and esd devices remain as significant sources of nonlinearity at very low currents. the voltage at vset can also be used to shield the highly sensitive inpt pin and its board trace from leakage currents, because the two pins operate at approximately the same potential. care must be taken to provide a low noise v set signal, since voltage noise at vset also appears at inpt and is transformed by the input compensation network into current noise. the ADL5315 provides a setpoint reference pin, sref, which can be connected to vset for standard 2-port mirror operation. v sref is maintained 1.0 v below v pos over temperature and is independent of input current. when using sref to set the input voltage, a capacitor should be placed between sref and ground to filter noise from sref as well as improve power supply rejection over frequency. a value of 2.2 nf, for example, combined with the 20 k output resistance at sref, creates a pole at approximately 3 khz. the voltage at the sref pin can be lowered to a desired fixed value with the use of a single external resistor from sref to ground. mismatch between on-chip and external resistors limits the accuracy of the resultant voltage. in addition, internal clamping to protect the precision bias limits the range. figure 20 shows an equivalent circuit model of the sref biasing. the schottky diode clamp protects the 50 a current source when sref is pulled to ground. when v sref is 1.2 v or higher, the 50 a current flows to the sref pin. the current is shunted away and does not appear at the sref pin for v sref < 0.6 v. the transition region is between 0.6 v and 1.2 v with a large uncertainty in the pull-down current. it is recommended that a 2-resistor divider from vpos (with no connection to sref) or another external bias be used to bias vref in this transition region. equations for the sref voltage with an external pull-down r ext follow: () v 1 v 1 k 2 2.,0. 0 ? + = sref pos ex t ext sref v v r r v v k 2 6.0, 0 + = sref pos ex t ext sref vv r r v where the 20 k is the process-dependent internal resistor. vset v pos c set ADL5315 05964-029 sref 50 a r ext 0.9v 20k figure 20. model of sref bias source with external pull-down
ADL5315 rev. 0 | page 10 of 20 the vset control is intended primarily to provide a dc bias voltage for the mirror input, but it is also well behaved in the presence of the v set transients. the rise time of v inpt is largely independent of input current because the mirror is capable of sourcing large currents to pull up the inpt pin. the fall time, however, is inversely proportional to i inpt because only i inpt is available to discharge the input compensation capacitor and other parasitics (see figure 11 ). the mirror output current can vary significantly from zero to several milliamps until v inpt is fully settled. noise performance the noise performance for the ADL5315, defined as the rms noise current as a fraction of the output dc current, generally improves with increasing signal current. this partially results from the relationship between the quiescent collector current and the shot noise in the bipolar transistors. at lower signal current levels, the noise contribution from the jfet amplifier and other voltage noise sources appearing at inpt contribute significantly to the current noise. filtering noise at vset, whether provided by sref or generated externally, as well as selecting optimal external compensation components on inpt, minimizes the amount of current noise at iout generated by the voltage noise at inpt. mirror response time the response time of i out to changes in i inpt is fundamentally a function of input current, with small-signal bandwidth increasing roughly in proportion to i inpt (see figure 10 ). the value of the external compensating capacitor on inpt strongly affects the i out response time (as well as the v set to v inpt fall time, as noted in the bias control interface section), although the value must be chosen to maintain stability and prevent noise peaking. input current limiting the ADL5315 provides a resistor-programmable input current limit with a fixed maximum of 16 ma for the rlim pin tied to vpos. the fixed maximum provides input short-circuit protection to ground. the current limit is defined as the current that forces v inpt to 0 v (when using a current source on the inpt pin). resistor r lim between the vpos and rlim pins controls the current limit according to k 3 v 48 + = lim lim r i over an r lim range of 0 to 45 k, corresponding to 16 ma down to 1 ma. larger values of r lim can be used for currents below 1 ma (down to approximately 250 a) with some degradation in accuracy. see figure 14 for more performance detail.
ADL5315 rev. 0 | page 11 of 20 applications the ADL5315 is primarily designed for wide dynamic range applications, simplifying power monitoring designs where access is only permitted to the cathode of a pin photodiode or receiver module. figure 22 shows a typical application where the ADL5315 is used to provide an accurate bias to a pin diode while simultaneously mirroring the diode current to be measured by a translinear logarithmic amplifier. in this application, the ADL5315 sets the bias voltage on the pin diode. this voltage is delivered at the inpt pin and is controlled by the voltage at the vset pin. vset is driven by the on-board reference v sref , which is equal to v pos ? 1 v. the input current, i inpt , is precisely mirrored at a ratio of 1:1 to the iout pin. this interface is optimized for use with any of adis translinear logarithmic amplifiers (for example, the ad8304 or ad8305 ) to offer a precise, wide dynamic range measurement of the optical power incident upon the pin. if a linear voltage output is preferred at iout, a single external resistor to ground is all that is necessary to perform the conversion. average power monitoring in applications where a modulated signal is incident upon the photodiode, the average power of the signal can be measured. figure 21 shows the connections necessary for using the ADL5315 in such a measurement system. the value of the capacitor to ground should be selected to eliminate errors due to modulation of the ADL5315 input current. voltage reference current limiting comm vset nc inpt data path linear voltage output i pd current mirror 1:1 ADL5315 4 2 7 sref 3 1 6 vpos pin 20k 5 rlim c set v pos 8 iout i pd tia 05694-010 figure 21. average power monitoring using the ADL5315 voltage reference current limiting comm vset nc inpt data path optical power translinear log amp ad8304, ad8305, etc. this connection is not necessary, but reduces errors due to leakage currents at low signal levels. i pd current mirror 1:1 ADL5315 4 2 7 sref 3 1 6 vpos v pos pin 20k 5 rlim r lim r lim = 48v i lim i lim = 1ma ? 16ma ? 3k 8 iout vsum inpt i pd tia v sref = v pos ? 1v v set = v inpt node voltages 05694-009 figure 22. typical application using the ADL5315
ADL5315 rev. 0 | page 12 of 20 translinear log amp interfacing the mirror current output, iout, of the ADL5315 is designed to interface directly to an analog devices translinear logarithmic amplifier, such as the ad8304 , ad8305 , or adl5306 . figure 24 shows the basic connections necessary for interfacing the ADL5315 to the ad8305. in this configuration, the designer can use the full current mirror range of the ADL5315 for high accuracy power monitoring. the measured rms noise voltage at the output of the ad8305 vs. the input current is shown in figure 23 , both for the ad8305 by itself and in cascade with the ADL5315. the relatively low noise produced by the ADL5315, combined with the additional noise filtering inherent in the frequency response characteristics of the ad8305, results in minimal degradation to the noise performance of the ad8305. careful consideration should be made to the layout of the circuit board in this configuration. leakage current paths in the board itself could lead to measurement errors at the output of the translinear log amp, particularly when measuring the low end of the ADL5315s dynamic range. it is recommended that when designing such an interface that a guard potential be used to minimize this leakage. this can be done by connecting the translinear log amps vsum pin to the nc pin of the ADL5315, with the vsum guard trace running on both sides of the iout trace. additional details on using vsum can be found in the ad8304 or ad8305 data sheets. the vset pin of the ADL5315 can be used in a similar fashion to guard the inpt trace. 5.5m 0 1n 1m i inpt (a) noise (v rms) 5.0m 4.5m 4.0m 3.5m 3.0m 2.5m 2.0m 1.5m 1.0m 0.5m 10n 100n 1 10 100 05694-012 ad8305 and ADL5315 ad8305 only figure 23. measured rms noise of ad8305 vs. ad8305 cascaded with ADL5315 voltage reference current limiting comm vset nc inpt data path ad8305 input compensation network i pd current mirror 1:1 ADL5315 4 2 7 sref 3 1 6 vpos pin 20k 5 rlim r lim i lim = 1ma ? 16ma 3v to 12v 8 iout i pd tia 1 2 3 4 11 scal 12 vout 10 bfin 9 vlog 5 v s u m 6 v n e g 7 v n e g 8 v p o s 1 5 c o m m 1 6 c o m m 1 4 c o m m 1 3 c o m m ad8305 vrdz vref iref inpt output v out = 0.2 log 10 (i pdm /1na) 200k 2k 4.7nf 1nf 1k 0.1 f 05694-011 c set v pos r lim = 48v i lim ? 3k figure 24. interfacing the ADL5315 to the ad8305 for high accuracy pin power monitoring
ADL5315 rev. 0 | page 13 of 20 extended operating range the ADL5315 is specified over an input current range of 3 na to 3 ma, but the device remains fully functional over the full eight decade range specified for adis flagship translinear logarithmic amplifier, the ad8304 (100 pa to 10 ma). figure 25 and figure 26 show the performance of the ADL5315 for this extended operating range vs. various temperature and supply conditions. this extended dynamic range capability allows the ADL5315 to be used in optical power measurement systems, precision test equipment, or any other system that requires accurate, high dynamic range current monitoring. 2.0 ?2.0 1n 100p 10m i inpt (a) linearity (%) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 10m 1n i out (a) 1m 100 10 1 100n 10n 100p 10n 100n 1 10 100 1m ?40 c +25 c +70 c +85 c 0 c +25 c, +70 c, +85 c, 0 c, ?40 c 05694-030 figure 25. extended operating range of 100 pa to 10 ma for multiple temperatures, normalized to 25c and i inpt = 3 a 2.0 ?2.0 1n 10m i inpt (a) linearity (%) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 10m 1n i out (a) 1m 100 10 1 100n 100p 10n 10n 100n 100p 1 10 100 1m i inpt vs. i out , all voltage conditions v pos = 2.7v, v set = v sref v pos = 5v, v set = 2v v pos = 5v, v set = v sref v pos = 8v, v set = 2v v pos = 8v, v set = v sref 05694-031 figure 26. extended operating range of 100 pa to 10 ma for multiple supply conditions, normalized to v pos = 5 v, v set = v sref and i inpt = 3 a using rlim as a secondary monitor the rlim pin can be used as a secondary linear output for monitoring input currents near the upper end of the ADL5315 current range. the rlim pin sinks a current approximately equal to i inpt /40. the voltage generated by this current through the series combination of an internal 3 k resistor and the external r lim is compared to a 1.2 v threshold and fed back to the mirror bias to limit i inpt . figure 27 shows the equivalent circuit and one method for using rlim to form a v set bias proportional to i inpt , also referred to as automatic photodiode biasing. this configuration is useful in pin photodiode systems to compensate for photo- diode equivalent series resistance (esr) while maintaining low reverse bias at low signal levels to minimize dark current. choosing r2 >> r lim minimizes impact on i lim and allows the resistor ratio, r2/r1, to be calculated based on maximum photodiode esr using the following simplified equation. r3r1rr2 r r40 r1 r2 lim li m pdmax = >> = , , where r pdmax is the maximum esr of the photodiode. for zero bias at zero input current, the sum of r lim and r3 must equal r1. for positive bias at zero input current, the sum of r lim and r3 should be greater than r1. the ratio of v pos to v set varies directly. for example, choosing r lim = 1.82 k (10 ma i lim ), r2 = 100 k, and r1 = 18.2 k compensates for photodiode esr up to 250 . a simple low voltage drop current mirror with a load resistor can replace the differential amplifier shown in figure 27 , although the resulting input current limit is less accurate and will vary with temperature. vpos mirror bias 05964-035 1.2v r2 r2 3k rlim rlim vset r3 r1 i inpt /40 v pos figure 27. providing automatic photodiode voltage biasing using rlim pin
ADL5315 rev. 0 | page 14 of 20 10m 1 10 100 1m 2.2 0 100p 1n i inpt (a) v set voltage (v) 05694-036 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 10n 100n figure 28. v set voltage vs. i inpt when rlim is configured for automatic photodiode biasing 2.2 0 02 1 1098 i inpt (ma) v set voltage (v) 1.4 1.6 1.8 2.0 1.2 0.2 0.4 0.6 0.8 1.0 34 5 67 05694-037 figure 29. v set voltage vs. i inpt when rlim is configured for automatic photodiode biasing figure 28 and figure 29 show the performance of the circuit in figure 27 . the reverse bias across the photodiode is held at a low value for small input currents to minimize dark current. the v set voltage increases in a linear manner at the higher input currents to maintain accurate photodiode responsivity. the minimum bias level for the configuration above is ~200 mv. characterization methods during characterization, the ADL5315 was treated as a precision 1:1 current mirror. to make accurate measurements throughout the six-decade current range, calibrated keithley 236 current sources were used to create and measure the test currents. measurements at low currents are very susceptible to leakage to the ground plane. to minimize leakage on the characterization board, the vset pin is connected to traces that buffer v inpt from ground. these traces are connected to the triax guard connector to provide buffering along the cabling. the primary characterization setup shown in figure 30 is used to perform all static measurements, including mirror linearity between i inpt and i out , v inpt variation vs. i inpt , supply current, and i inpt current limiting. component selection of the characterization board is similar to that of the evaluation board, except that triax connectors are used instead of sma. to measure pulse response, noise, and small signal bandwidth, more specialized test setups are used. keithley 236 keithley 236 05694-025 ADL5315 characterization board vpos vset sref comm iout dc supplies/dmm inpt figure 30. primary characterization setup the setup in figure 31 is used to measure the output current noise of the ADL5315. batteries are used in numerous places to minimize introduced noise and remove the uncertainty resulting from the use of multiple dc supplies. in application, properly bypassed dc supplies provide similar results. the load resistor is chosen for each current to maximize signal-to-noise ratio while maintaining measurement system bandwidth (when combined with the low capacitance jfet buffer). the custom lna is used to overcome noise floor limitations in the hp89410a signal analyzer.
ADL5315 rev. 0 | page 15 of 20 05694-028 r input fet buffer vector signal analyzer hp89410a ADL5315 vpos sref vset +12v ?12v inpt iout r load 2.2nf lna 1.5v + ? + ? 1.5v 9v + ? 1.5v + ? ? + 9v figure 31. configuration for noise spectral density and wideband current noise figure 32 shows the configuration used to measure the pulse response of i inpt to i out . to create the test current pulse, q1 is used in a common base configuration with the agilent 33250a pulse generator. the output of the 33250a is a negative biased square wave with an amplitude that results in a one decade current step at i out . r c is chosen according to what current range is desired. for 30 a and lower, the ad8067 fet input op amp is used in a transimpedance amplifier configuration to allow for viewing on the tds5104 oscilloscope. for signals greater than 30 a, the ada4899-1 replaced the ad8067 to avoid limiting the bandwidth of the ADL5315. the configuration in figure 33 is used to measure v inpt while v set is pulsed. q1 and r c are used to generate the operating current on the inpt pin. an agilent 33250a pulse generator is used on the vset pin to create a 0.0 v to 4.0 v square wave. the setup in figure 34 was used to measure the small signal ac response from i inpt to i out . the ad8138 differential amplifier was used to couple the ac and dc signals together. the ac signal was modulated to a depth of 5% of full scale over frequency. the voltage across r f sets the dc operating point of i inpt . the values of r f are chosen to result in decade changes in i inpt . the ada4899-1 op amp is used as a transimpedance amplifier for all current conditions. tds5104 oscilloscope ADL5315 evaluation board inpt vpos vset sref comm iout dc supplies/dmm r c r c agilent 33250a pulse generator q1 05694-024 figure 32. configuration for pulse response of i inpt to i out 05694-026 r c q1 tds5104 oscilloscope ADL5315 evaluation board vpos sref comm iout dc supplies/dmm inpt vset agilent 33250a pulse generator keithley 236 figure 33. configuration for pulse response from v set to v inpt network analyzer output r ba power splitter ad8138 eval board ++ ?? ADL5315 evaluation board inpt 50 05694-027 iout r f r f vpos vset sref comm dc supplies/dmm figure 34. configuration for small-signal ac response
ADL5315 rev. 0 | page 16 of 20 evaluation board ADL5315 inpt i pd sref vpos v pos v set comm 1 3 6 vset 2 4 7 nc 8 iout i out 5 rlim gnd sw1 r3 0 l1 0 c2 0.01 f c1 0.01 f c3 390pf c4 open r5 open r2 10k s ref r4 4k r1 100 05694-013 figure 35. evaluation board schematic (rev. a) table 4. evaluation board (rev. a) configuration options component function default conditions vpos, gnd supply and ground connections. not applicable input, l1, c4 input interface: the evaluation board is conf igured to accept an input current at the sma connector labeled input. filtering of th is current can be done using l1 and c4. l1 = 0 (size 0805) c4 = open (size 00603) r4, c3 input compensation. provides essential hf co mpensation at the inpt pin. c3 = 390 pf (size 0805) r4 = 4.02 k (size 0402) sref, vset, sw1, r1, r6, r7 inpt bias voltage. the dc voltage applied to vset determines the voltage at inpt, v set = v inpt . connecting sref to vset sets the bias at inpt to be 1 v below v pos . opening sw1 allows for vset to be driven externally via the sma connector. sw1 = closed r1 = 100 (size 0402) r6 = r7 = 0 (size 0402) iout, r5 output/mirror current interface: the output cu rrent at the sma connector labeled iout is equal to the value at inpt. r5 allows a resistor to be installed for applications where a scaled voltage referenced to ipd is desirable instead of a current. r5 = open (size 0603) r2 current limiting. an external resistor to vp os sets the current limit at inpt from 1 ma to 16 ma. i lim = 48 v/(r lim + 3 k). the evaluation board is configured such that i lim = 3.7 ma. r2 = 10 k (size 0402) c1, c2, r3 supply filtering/decoupling. c1 = 0.01 f (size 0402) c2 = 0.1 f (size 0603) r3 = 0 (size 0805) 05694-014 figure 36. component side layout 05694-015 figure 37. component side silkscreen
ADL5315 rev. 0 | page 17 of 20 outline dimensions 0.30 0.23 0.18 seating plane 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 1.89 1.74 1.59 0.50 bsc 0.60 0.45 0.30 0.55 0.40 0.30 0.15 0.10 0.05 0.25 0.20 0.15 bottom view * 4 1 58 3.25 3.00 2.75 1.95 1.75 1.55 2.95 2.75 2.55 pin 1 indicato r 2.25 2.00 1.75 top view 0.05 max 0.02 nom 12 max exposed pad figure 38. 8-lead lead frame chip scale package [lfcsp_vd] 2 mm 3 mm body, very thin, dual lead (cp-8-1) dimensions shown in millimeters ordering guide model temperature range package description package option branding ADL5315acpz-r7 1 C40c to +85c 8-lead lfcsp_vd cp-8-1 q0 ADL5315acpz-wp 1 , 2 C40c to +85c 8-lead lfcsp_vd cp-8-1 q0 ADL5315-eval evaluation board 1 z = pb-free part. 2 wp = waffle pack
ADL5315 rev. 0 | page 18 of 20 notes
ADL5315 rev. 0 | page 19 of 20 notes
ADL5315 rev. 0 | page 20 of 20 notes ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05694C0C10/05(0)

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